Three-dimensional (3-D) integration with through-silicon via (TSV) is a design technique that stacks multiple semiconductor dies. Compared to conventional two-dimensional (2-D) integration, it is capable of providing heterogeneous integration, high performance, high bandwidths, low power consumption, and small form factor. A main challenge that 3-D integration is faced with is the test issue.
A conventional test flow for a 3-D chip includes three phases: known-good die (KGD) test, known-good stack (KGS) test, and final test.
The test flow for a 3-D random access memory (RAM) is no different from the above. After manufacturing a memory wafer, the KGD test for the wafer is performed by a chip probe to determine which memory dies are functional, so as to prevent yield loss of the 3-D RAM caused by stacking bad dies.
In the process of TSV manufacturing and die stacking, it is possible that the good dies become bad. Therefore, defects causing the die stack to fail ought to be filtered out by performing the KGS test.
When all dies are stacked, the final test is performed to ensure that the stacked 3-D RAM is functional.
When performing the KGD test, the TSV cannot be easily tested or contacted directly by the chip probe, and additional test pads are required for assisting related KGD test process. In the 3-D RAM, memory dies are connected via the TSVs to signal terminals, power terminals, and ground terminals. The diameter of the TSV ranges from 1 μm to 10 μm, implying that the test cost will significantly increase if the KGD test is to be performed by directly contacting the TSVs by the chip probe.
A conventional solution is adding a test pad on the dies. The test pads are tailored for assisting the KGD test. Through the test pads, control signals, power and ground terminals can be provided by the current chip probe technique rather than needing a costly chip probe operable with respect to the diameter of the TSV. However, the number of test pads inevitably affects test cost and test time. Further, in the final test, since the dies are already stacked, a direct access to each of the stacked memory dies is also made quite challenging.
Therefore, a 3-D integrated circuit needs standardized test interface for controlling internal test circuits, so as to effectively shorten test time and reduce the number of test pads, as well as to facilitate test integration of different manufacturers.
In a current 3-D RAM, each of the memory dies includes a built-in self-test (BIST) circuit which inherits a conventional test method (to be described shortly) of a memory embedded in a 2-D system-on-chip (SoC). Each of the memory dies further includes a controller with a standardized test interface for controlling the BIST circuit on the same die. The lowermost memory die in the stack may further include a logic circuit such as a processor. The processor can be wrapped with an IEEE 1500 test wrapper for facilitating the test process. The IEEE 1500 test wrapper may have a different operating clock from that of the BIST circuit—the BIST circuit usually operates at a high-speed clock to match a normal operating speed, whereas the IEEE 1500 test wrapper usually operates at a low-speed clock for easing the requirements of the test equipment, as it cooperates with a scan test.
The memory of 2-D SoC generally utilizes a BIST circuit to reduce the high test cost associated with high-speed test equipment. Low-speed test equipment operating at a low speed clock provides commands to a controller of the BIST circuit. In response, the controller sends commands to a test pattern generator (TPG) of the BIST circuit for a memory bank under test. The TPG generates memory read/write address and data (0 or 1) to test the memory bank at a high-speed clock. When a result differs from an expected value, the TPG sends an error message back to the controller to report to the low-speed test equipment.
FIG. 1 shows a timing diagram of a conventional BIST circuit in a 3-D RAM. TCK0.TN and TCK1.TN respectively represent a low-speed test clock adopted by a controller of the BIST circuit, and a high-speed test clock adopted by a TPG, where N is a positive integer. When the 3-D RAM performs a parallel test, the BIST circuits on different dies execute a user test command synchronously. When a conventional BIST circuit structure is utilized, a clock skew S1 is sustainable during KGS test and final test. However, when the low-speed clock signal, based on which stacked die the controller operates, is affected by the variation of the delay incurred by the TSV, an unexpected skew is also introduced in the low-speed clock signal received by the controller of the BIST circuit, as indicated by a skew S2. Thus, a delay or a skew between enable signals (e.g., TPG_EN.T1 and TPG_EN.T2) received by the TPGs of the BIST circuits of different dies may reach one or more than one high-speed clock cycles, as indicated by a skew S3. Consequently, the test may not be performed synchronously and the overall test quality is degraded.
Considering the structure of the 3-D RAM, each independent channel connects to memory banks on different dies through the TSVs. When performing the KGS test or the final test on the 3-D RAM, some of these memory banks may need to be tested synchronously. In an extreme case, all memory banks of an uppermost die (assuming that the uppermost die is located farthest from a power supply) need to be tested synchronously. Further, because the power consumptions of write and read operations can differ, the BIST circuit needs to guarantee that all memory banks perform read or write operations at the same time to ensure the test is performed in the worst-case condition. Consequently, the memory banks on different dies ought to be activated simultaneously during the test process. That is to say, the test quality of the 3-D RAM is guaranteed only when all corner-case conditions are tested.